- systolic array architecture
- архитектура на основе систолических матриц
The New English-Russian Dictionary of Radio-electronics. F.V Lisovsky . 2005.
The New English-Russian Dictionary of Radio-electronics. F.V Lisovsky . 2005.
Systolic array — In computer architecture, a systolic array is a pipe network arrangement of processing units called cells. It is a specialized form of parallel computing, where cells ( i.e. processors), compute data and store it independently of each other.… … Wikipedia
Instruction Systolic Array — Ein Instruction Systolic Array (ISA) ist im Gegensatz zum Systolischen Array ein gitterartig verbundenes Netzwerk von einfachsten Berechnungseinheiten (Prozessoren), das dadurch gekennzeichnet ist, dass die Befehle von einer Ecke in synchronen… … Deutsch Wikipedia
Supersystolischer Array — Systolischer Array ist die Bezeichnung für ein Pipe Netzwerk von DPUs (Data Path Units), meist in Matrix Anordnung, durch welches Datenströme hindurchgetaktet werden im Gegensatz zum Instruction Systolic Array, durch den Befehle hindurchgeschickt … Deutsch Wikipedia
Systolischer Array — ist die Bezeichnung für ein Pipe Netzwerk von DPUs (Data Path Units), meist in Matrix Anordnung, durch welches Datenströme hindurchgetaktet werden im Gegensatz zum Instruction Systolic Array, durch den Befehle hindurchgeschickt werden. Der… … Deutsch Wikipedia
Dataflow architecture — is a computer architecture that directly contrasts the traditional von Neumann architecture or control flow architecture. Dataflow architectures do not have a program counter, or (at least conceptually) the executability and execution of… … Wikipedia
Transport triggered architecture — The transport triggered architecture (TTA) is an application specific instruction set processor ( ASIP ) architecture template that allows easy customization of microprocessor designs. The basic idea of transport triggering is to allow programs… … Wikipedia
Reconfigurable computing — is a computer architecture combining some of the flexibility of software with the high performance of hardware by processing with very flexible high speed computing fabrics like field programmable gate arrays (FPGAs). The principal difference… … Wikipedia
Duncan's Taxonomy — is a classification of computer architectures, proposed by Ralph Duncan in 1990.[1] Duncan proposed modifications to Flynn s taxonomy[2] to include pipelined vector processes.[3] Contents 1 Taxonomy … Wikipedia
Monica S. Lam — Monica Sin Ling Lam is a professor in the Computer Science Department at Stanford, and Founder and Chief Scientist of MokaFive.[1] Contents 1 Professional biography 2 Bibliography 3 Awards … Wikipedia
RISC — У этого термина существуют и другие значения, см. RISC (значения). RISC (англ. restricted (reduced) instruction set computer[1][2] компьютер с сокращённым набором команд) архитектура процессора, в которой быстродействие… … Википедия
Reiner Hartenstein — (born December 18, 1934 in Berlin) is a German computer scientist. He is a professor of Computer Science (Informatik) at the University of Kaiserslautern. He earned all his academic degrees, including his Ph. D. (Dr. Ing.), from the EE department … Wikipedia